Error correction methods and apparatuses using first and second decoders

ABSTRACT

Apparatuses and methods for error correcting data are provided. A first error correction code (ECC) decoder is configured to decode a first codeword to provide a first result and to decode a second codeword to provide a second result. The decoder is configured to run up to a particular number of iterations to provide each of the results. A second ECC decoder is configured to decode a third codeword to provide decoded data, wherein the third codeword comprises the first result and the second result. An evaluation module is configured to initiate a recovery scheme responsive to the decoded data including an error.

BACKGROUND

1. Field

The present application relates generally to error correction methods and memory devices.

2. Description of the Related Art

Error correction codes (ECCs) have been used to detect and/or correct errors in data read from memory devices. Examples of such codes include, but are not limited to Bose-Chaudhuri-Hocquenghem (BCH) codes, Hamming codes, and Reed-Solomon (RS) codes. Decoders configured to decode data encoded with such codes (hereinafter referred to as a “codeword”) can be incorporated in, for example, controllers, such as an internal controller of a memory device (e.g., a managed NAND device) and/or an external controller configured to be coupled to a memory device(s), among other apparatuses.

In some memory devices, hard data and/or soft data can be read (e.g., sensed and/or transferred) from the memory cells of the memory devices. Hard data can indicate the detected data state of a memory cell that has been read. For example, hard data can indicate whether such a memory cell was sensed to be in a data state representing a binary value of “1” or a data state representing a binary value of “0” (for the page being read). Meanwhile, soft data can indicate more precisely where within the detected data state the memory cell was sensed. For example, soft data can indicate whether such a memory cell was sensed to be within a first portion, a second portion, or a third portion of the detected data state. Some current state of the art ECC decoders, such as low density parity check (LDPC) code decoders, can take advantage of soft data when decoding a codeword. However, working with soft data has various challenges. For example, it may take longer to sense data including soft data than to sense data including only hard data. As another example, transferring soft data from a memory device through an interface, such as the Open NAND Flash Interface (ONFI), can result in a high throughput penalty as more bits of data are transferred than if only hard data was transferred.

Conventional LDPC decoders run a sufficient number of iterations to correct errors in a codeword. As a result, the LDPC decoder can utilize significant power, since running, for example, two iterations will consume approximately twice as much power as running a single iteration. In applications having extremely tight power budgets, this can prevent or inhibit employing a powerful LDPC decoder. In addition, when the input to the LDPC decoder consists of only hard data, the LDPC decoder may need to run more iterations than it would otherwise need if soft data was also input to the LDPC decoder. Also, a different number of iterations may need to be run depending on the number of errors in the codeword, which can pose a serious problem if the application needs a “sustained throughput” and does not tolerate variations in the throughput.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow diagram of an example method for error correcting data in accordance with certain embodiments described herein.

FIG. 2 schematically illustrates an example apparatus configured to perform a method for error correcting data in accordance with certain embodiments described herein.

FIG. 3 schematically illustrates an outer codeword and two inner codewords in accordance with certain embodiments described herein.

FIG. 4 is a graph of the performance of an example controller utilizing a single iteration of LDPC inner decoding with BCH outer decoding in accordance with certain embodiments described herein.

DETAILED DESCRIPTION

Certain embodiments described herein are particularly compatible for use with flash memory, a form of erasable and reprogrammable non-volatile memory. In a flash memory, memory cells are arranged in “blocks” for erasure. After a block has been erased, it is ready for programming if desired. NOR flash memory is a type of flash memory that offers access to individual memory cells for retrieval of data, but has relatively low density. NAND flash memory is a type of flash memory that offers relatively high density. The high density is achieved in part by forming strings of memory cells connected in series. In addition, with NAND flash memory, data is accessed (e.g., programmed and read) in relatively large groups of bytes, such as a page of data. For example, a page can correspond to a row or to a portion of a row of memory cells in an array. Flash memory can be used in many apparatuses, including but not limited to solid state drives (replacements for hard drives), USB flash drives or thumb drives, mobile phones, digital cameras, digital media players, games, memory cards, navigation devices, personal digital assistants, computers, or the like. Although many of the embodiments described herein are discussed in the context of flash memory, other forms of memory might also benefit from the technology discussed herein.

Some memory devices and/or controllers are capable of operating in a hard data only mode, where only hard data is sensed and/or transferred, and a soft data mode(s), where soft data, corresponding to the hard data, is sensed and/or transferred along with the hard data. In view of the challenges discussed herein, it can be desirable to operate in the hard data only mode as much as possible. For example, a memory device and/or controller can generally be operated in the hard data only mode, but the memory device and/or controller can switch to the soft data mode in certain circumstances, such as after a particular number of program-erase (P/E) cycles and/or when operated in certain retention modes. Furthermore, the default operating mode of a memory device and/or controller in some embodiments can be the hard data only mode.

Concatenated coding schemes, in which multiple codes are concatenated (e.g., LDPC and BCH codes), have been proposed, such as in, for example, U.S. Pat. Appl. Publ. No. 2009/0013234; E. Yeo, “An LDPC-Enabled Flash Controller in 40 nm CMOS,” Flash Memory Summit 2012, Santa Clara, Calif.; M. Jedrak, “ECC in NAND Flash Controller,” Flash Memory Summit 2012, Santa Clara, Calif.; N. Xie et al., “Concatenated Low-Density Parity-Check and BCH Coding System for Magnetic Recording Read Channel with 4 kB Sector Format,” IEEE Trans. On Magnetics, Vol. 44, No. 12, December 2008, pp. 4784-4789. In certain embodiments described herein, the resources (e.g., ECC bits) of a first code (e.g., BCH code) are pooled for multiple inner codewords (e.g., LDPC codewords), such as to more efficiently utilize the redundancy of the first code by offering the pooled first code resources to codewords of a second code (e.g., LDPC code) that may be in need of extra correction. For example, in at least some of the disclosed embodiments, an inner decoder (e.g., a LDPC decoder) can run up to a particular number of iterations (e.g., a single iteration) to do as much error correction as possible with the limited number of iterations. An outer decoder (e.g., a BCH decoder) can be used to correct residual errors left after the inner decoder (e.g., the LDPC decoder) runs its limited number of iterations. The outer decoder can also deal with potential error floor or miscorrection issues arising from the use of the inner code decoder. For example, the inner decoder may decode the input data to a valid codeword that is different than the correct codeword or may become trapped, and the outer decoder can potentially correct these errors. If the default concatenated coding scheme is unable to correct (e.g., clear) all the errors, the controller and/or memory device can access the memory cells again to read soft data, provide the soft data to the inner decoder, and allow the inner decoder to run more than the particular number of iterations.

If performance of a scheme when only hard data is input to a decoder (hereinafter “hard data performance”) was the only performance criterion, then a trade-off could be made between the redundancies of the inner code (e.g., LDPC code) and the outer code (e.g., BCH code) to improve the performance. For example, the LDPC redundancy could be reduced and the BCH redundancy could be increased while keeping the total ECC budget the same. The number of available ECC bits used for LDPC can be reduced and instead these ECC bits can be devoted to BCH by allocating more of the ECC resources to BCH (thereby providing an increased T level), and allocating less of the ECC resources to LDPC. However, doing so may reduce the soft data performance of such a scheme (e.g., the performance of such a scheme when soft data is also input to the decoder and the decoder runs multiple iterations). Given that the total bits/bytes written (TBW) is a function of recovery performance, any hard input performance improvement should not jeopardize the recovery performance which utilizes soft data.

On the other hand, if soft data performance is the only important metric and power is not a constraint (such that multiple decoder iterations could be run) and soft data is always available, from a raw bit error rate (RBER) point of view, it could be advantageous to use the whole ECC budget for LDPC code (e.g., using all the available ECC bits for LDPC).

In certain schemes with a limited number of iterations (e.g., a single iteration), the inner decoder (e.g., a LDPC decoder) might be unable to correct all the errors in an inner codeword, except for very low RBERs. The outer decoder (e.g., a BCH decoder) can thus be used to correct residual errors left after the limited number of iterations of the inner decoder (e.g., the LDPC decoder) are run, but an inefficiency can result from a concatenated ECC scheme in which the inner decoder (e.g., LDPC decoder) does not fully utilize the correction capability of the outer decoder (e.g., the T-level of the BCH code), as the following example illustrates.

In an example scenario, four LDPC codewords are used:

Codeword 1 has 10 bit errors after decoding using the LDPC decoder

Codeword 2 has 25 bit errors after decoding using the LDPC decoder

Codeword 3 has 15 bit errors after decoding using the LDPC decoder

Codeword 4 has 5 bit errors after decoding using the LDPC decoder

These four codewords have a total of 55 bit errors. If each LDPC codeword is protected by a respective BCH codeword, and assuming that the BCH code has a T-level of 20, the concatenated coding scheme could correct the three LDPC codewords having fewer bit errors than the T-level of the BCH code, but would not correct codeword 2 since it has more bit errors than the T-level of the BCH code.

Instead, in certain embodiments, multiple LDPC codes are protected with a single larger BCH codeword (i.e., in comparison to the size of a codeword used in the “respective” BCH codeword scheme discussed in the previous paragraph), so that the BCH redundancy is used more efficiently. In other words, the outer code (e.g., BCH code) redundancy (e.g., ECC bits for the BCH code) is pooled for multiple codewords of the inner code (e.g., LDPC code). Thus, for N inner codewords that are protected with a single larger outer codeword, if all but one of the inner codewords is fully corrected after decoding with the inner decoder, then the inner codeword still having errors will have the correction capability of approximately N times the rate of the outer code for the respective codeword scheme. For example, assuming that the four LDPC codewords described above are protected using a single larger BCH codeword with the same redundancy (e.g., the number of BCH ECC bits in the single BCH codeword is the same as the total number of BCH ECC bits used in the respective codeword scheme), the BCH code can have a T-level that is slightly less than 4*20=80. In such an example case, all four inner LDPC codewords could be corrected by such a concatenated coding scheme.

Certain such embodiments utilize the redundancy (e.g., ECC bits) of the outer code (e.g., BCH code) more efficiently, so a higher RBER number can be supported as compared to a “respective” codeword concatenation scheme. In certain embodiments, a higher supported RBER number for the hard data only mode will advantageously reduce the need to operate in a soft data mode. In addition, the soft data RBER performance in certain embodiments will be unaffected, unlike other schemes that can potentially improve hard data performance while deteriorating soft data performance. Also, certain embodiments described herein are scalable. For example, depending on the hardware constraints, as few as two inner codewords can be protected by the same outer codeword. Pooling outer code resources for more than two inner codewords can translate into a higher supported RBER number for hard data performance.

In certain embodiments in which N inner codewords are protected by a single outer codeword, initial inner decoding latency for the scheme can be higher (e.g., instead of a single inner codeword time latency, a time latency of N times the single inner codeword time latency). The N decoded results provided by the inner decoder (for the N inner codewords) can be buffered before the outer decoder starts decoding, which can result in higher buffering. For example, even if only a single inner codeword worth of data is desired to be accessed, N inner codewords will be decoded since the outer decoder will need the results of all N inner codewords from the inner decoder. In certain embodiments, the correction capability (e.g., T-level) of a scheme using a single larger outer codeword can be slightly less than N times the correction capability of a scheme using N outer codewords that match the size of N inner codewords. Slight performance degradation may result at very high RBER levels that are outside the typical operating range.

FIG. 1 is a flow diagram of an example method 100 for error correcting data in accordance with certain embodiments described herein. In an operational block 110, the method 100 comprises reading a first codeword from memory. In an operational block 120, the method 100 further comprises reading a second codeword from the memory. In an operational block 130, the method 100 further comprises decoding the first codeword using a first decoder to provide a first result without inputting soft data to the first decoder. The first decoder runs up to a particular number of iterations to provide the first result. In an operational block 140, the method 100 further comprises decoding the second codeword using the first decoder to provide a second result without inputting soft data to the first decoder. The first decoder runs up to the particular number of iterations to provide the second result. In an operational block 150, the method 100 further comprises decoding a third codeword using a second decoder to provide decoded data. The third codeword comprises the first result and the second result. In an operational block 160, the method 100 further comprises performing a recovery scheme if the decoded data includes an error.

In certain embodiments, the memory comprises flash memory having a plurality of memory cells. Reading the first and second codewords from the memory in the operational blocks 110 and 120 of certain embodiments comprises detecting (e.g., sensing) data states of a plurality of memory cells storing the first codeword and the second codeword and transferring hard data indicating the detected states to a controller. In certain embodiments, more than two codewords can be detected (e.g., sensed) in the operational blocks 110, 120. For example, reading the first and second codewords can be performed as part of a process of detecting (e.g., sensing) data states of a page of memory having a plurality of codewords. The detected (e.g., sensed) data states of the page can then be transferred (e.g., via an ONFI interface) to the controller.

Decoding the first and second codewords using a first decoder in the operational blocks 130 and 140 of certain embodiments can include using an inner decoder to decode inner codewords consisting of the hard data read in the operational blocks 110 and 120 using a first ECC decoding procedure. Examples of the first ECC decoding procedure include but are not limited to an LDPC code decoding procedure (e.g., performed by an LDPC decoder) and/or a Turbo code decoding procedure (e.g., performed by a Turbo decoder) and/or a turbo-product code decoding procedure (e.g., performed by a turbo-product decoder) and/or a lattice code decoding procedure (e.g., performed by a lattice decoder) and/or a polar code decoding procedure (e.g., performed by a polar decoder) and/or a general linear block code decoding procedure (e.g., performed by a general linear block decoder). In certain embodiments, the particular number of iterations run up by the first decoder in the first ECC decoding procedure to provide either the first result or the second result is one, while in certain other embodiments, the particular number of iterations is two, three, or more. Having the particular number of iterations equal to one, which limits the first ECC decoding procedure to a single iteration, can provide the advantage of reduced power consumption as compared to allowing the decoder to run a higher number of iterations.

The results of decoding the first and second codewords can be grouped together to form a third codeword which can be decoded in the operational block 150. For example, the first result of decoding the first codeword can be buffered while the second codeword is decoded, such that the first and second results provided in the operational blocks 130 and 140 can be grouped together (e.g., concatenated and/or interleaved) to form a third codeword. Although examples are primarily discussed herein in which two inner codewords are grouped together to form an outer codeword, embodiments are not limited thereto. For example, other embodiments might group together 3, 4, 5, 6, 7, 8 or more inner codewords. One or more of the inner codeword can protect parity bits of the outer code as well as the user data bits. For example, as schematically illustrated by FIG. 3, an inner LDPC codeword can protect all the BCH parity bits. However, in certain other embodiments, the BCH parity can be interleaved or can be separated and spread to some or all of the other inner codewords. In certain embodiments in which each inner codeword (e.g., the first codeword and the second codeword) has a width of 512 bytes, 1 kilobyte, or 2 kilobytes, the outer codeword (e.g., the third codeword) can have a width of, for example, 1, 2, 4, 6, 8, 10, 12, 14, or 16 kilobytes.

Decoding a third codeword using a second decoder to provide decoded data in the operational block 150 of certain embodiments can include using an outer decoder to decode the third codeword formed by the first and second results provided in the operational blocks 130 and 140. Examples of the second ECC decoding procedure include but are not limited to a BCH code decoding procedure (e.g., performed by a BCH decoder) and/or a RS code decoding procedure (e.g., performed by a RS decoder) and/or a bit-based decoding procedure (e.g., performed by a bit-based decoder) or a symbol-based decoding procedure (e.g., performed by a symbol-based decoder). For example, the BCH code decoding procedure can have a correction capability (T-level) in a range between 20 and 160, in a range having a lower bound of 20, 30, 40, 50, or 60, having an upper bound of 100, 110, 120, 130, 140, 150, or 160, or having any combination of these lower bounds and upper bounds.

An evaluation of whether the decoded data includes an error in the operational block 160 of certain embodiments can comprise generating a signal indicative of whether the decoded data includes at least one bit error or whether the decoded data does not include at least one bit error. In certain embodiments, the evaluation can be performed by the outer decoder (e.g., BCH decoder), while in certain other embodiments, the evaluation can be performed by an evaluation module separate from the outer decoder, with the evaluation module utilizing error detection codes (EDCs) such as cyclic redundancy check (CRC) codes.

In operational block 160, a recovery scheme can be performed if the decoded data includes an error. For example, soft data corresponding to the first and second codewords can be read from the memory (e.g., either re-reading the first and second codewords along with the soft data and/or just reading the soft data or just transferring soft data previously sensed by the memory device, but not originally transferred when in the hard data only mode). The first and second codewords can then be re-decoded by the first (e.g., inner) decoder using the soft information and/or allowing the first decoder to run for more than the particular number of iterations. Third and fourth results provided by re-decoding the first and second codewords, respectively, can then be grouped together as a fourth codeword. The second (e.g., outer) decoder can then decode the fourth codeword to provide re-decoded data.

In certain embodiments, the method 100 for error correcting data has a total ECC budget (e.g., total number of ECC bits in a page and/or block), divided between the first ECC scheme (e.g., LDPC code) and the second ECC scheme (e.g., BCH code). The ECC budget can be expressed as the maximum allowed redundancy for the error correction codes. For some systems, the ECC budget is determined by the spare portion (e.g., the size of spare area of a page) of the non-volatile memory system (e.g., flash memory device). For example, the total ECC budget can be in a range between 5% and 20% of the bits in a page or block of data, in a range between 5% and 15% in a page or block of data, or in a range between 7% and 12% in a page or block of data. In certain embodiments, the first ECC scheme (e.g., LDPC code) can use between two-thirds and nine-tenths of the total ECC budget. For example, for a total ECC budget of 10% of a page or block of data, the first ECC scheme can use between 67% and 90% of the total ECC budget (e.g., 8% of a page or block of data). In certain embodiments, the second ECC scheme (e.g., BCH code) can use between one-tenth and one-third of the total ECC budget. For example, for a total ECC budget of 10%, the second ECC scheme can use between 10% and 33% of the total ECC budget (e.g., 2% of a page or block of data).

FIG. 2 schematically illustrates an apparatus in the form of a controller 200 coupled to memory 210 in accordance with certain embodiments described herein. As understood, among other possibilities, the memory 210 can be a memory device (e.g., a NAND flash memory device or a plurality of NAND flash memory devices) and the controller 200 can be an external controller coupled to the memory device(s), or memory 210 can be an array of memory cells and controller 200 can be an internal controller coupled to the array (e.g., where the combination of the internal controller and array form part of a memory device). Examples of devices comprising a controller 200 in accordance with certain embodiments described herein include but are not limited to solid state drives, USB flash drives, thumb drives, mobile phones, digital cameras, digital media players, games, memory cards, navigation devices, personal digital assistants, computers, or the like.

The controller 200 of certain embodiments has a first ECC decoder 230 configured to decode (at least) first and second codewords read from the memory 210 and provide first and second results, respectively. The first ECC decoder 230 can run up to a particular number of iterations to decode the first and second codewords. For example, in certain embodiments, the first ECC decoder 230 can be a single decoder that operates on the inner codewords serially, and that runs up to a particular maximum number of iterations for each of the codewords. For example, the first ECC decoder 230 can comprise a single decoder configured to generate multiple codewords serially, using up to a particular maximum number of iterations for each of the codewords. In certain other embodiments, the first ECC decoder 230 can comprise multiple decoders that operate on the inner codewords in parallel with one another, with the inner decoders running up to a particular maximum number of iterations for each of the codewords. For example the first ECC decoder 230 can comprise multiple decoders configured to generate multiple codewords in parallel, using up to a particular maximum number of iterations for each of the codewords The controller 200 further comprises a second ECC decoder 240 configured to decode a third codeword (that comprises the first and second results) to provide decoded data. The controller 200 further comprises an evaluation module 250 configured to initiate a recovery scheme (e.g., by responding to an error in the decoded data by generating a signal configured to initiate the recovery scheme). One such recovery scheme might involve reading soft data (corresponding to the hard data constituting the first and second codewords) from the memory and re-decoding the first and second codewords using the soft data.

The third codeword of certain embodiments can comprise an outer codeword comprising a plurality of inner codewords, including the first and second codewords. FIG. 3 schematically illustrates an outer codeword 300 and two inner codewords 310 in accordance with certain embodiments described herein. The outer codeword 300 can comprise a number of outer ECC bits (e.g., BCH ECC bits) and a number of user data bits. Each inner codeword 310 can comprise a number of user data bits and a number of inner ECC bits (e.g., LDPC ECC bits). The second ECC decoder 240 of certain embodiments can be configured to use the outer ECC bits to correct errors in the user data bits and the first ECC decoder 230 can be configured to use the inner ECC bits to correct errors in the user data bits and outer code ECC bits. In certain embodiments, the number of inner ECC bits is greater than the number of outer ECC bits (e.g., about four times greater). In certain embodiments, the number of inner and outer ECC bits in the third codeword comprises about 10% of a number of bits in a page of memory.

The controller 200 has an input 220 configured to receive codewords read from the memory 210. In certain embodiments, the input 220 comprises an open NAND flash interface (ONFI), while in certain other embodiments, the input comprises other types of interfaces. In certain embodiments, the first ECC decoder 230 comprises a LDPC decoder and the second ECC decoder 240 comprises a BCH decoder. The evaluation module 250 of certain embodiments is a separate component from the second ECC decoder (e.g., which utilizes an error detection code such as CRC), while in certain other embodiments, the evaluation module 250 is a component of the second ECC decoder 240 or the second ECC decoder 240 is a component of the evaluation module 250.

In an embodiment where the second ECC decoder comprises a BCH decoder, the BCH decoder can be configured to calculate a syndrome to determine whether the third codeword includes any errors. For example, a zero syndrome may indicate that the third codeword includes no errors. If the syndrome is non-zero, such a decoder may be configured to determine the number of errors in the third codeword and the location of those errors in the third codeword. For example, the decoder may determine an error locator polynomial from the syndrome in accordance with an algorithm, such as the Berlekamp-Massey algorithm or the Peterson-Gorenstein algorithm, and calculate the roots of the error locator polynomial to identify the location(s) of the error(s) in the third codeword. In the case of a binary BCH, a decoder can invert a respective bit of data at each of those locations in the third codeword to correct the error, thus providing decoded data. If non-binary BCH codes are used, a decoder can calculate the error values at those locations and use the calculated error values to correct the third codeword, thus providing decoded data.

In certain embodiments in which the apparatus further comprises memory (e.g., a memory device, examples of which include but are not limited to a NAND Flash memory device which can be coupled to the controller 250 through an ONFI interface), the memory can be coupled to a controller 200 comprising the first ECC decoder 230, the second ECC decoder 240, and the evaluation module 250. The controller 200 can be configured to read the first and second codewords from the memory while operating in a hard data only mode. In certain embodiments, the evaluation module 250 being configured to initiate a recovery scheme comprises the evaluation module 250 being configured to switch an operating mode of the controller 250 from the hard data only mode to a soft data mode. In certain embodiment, while operating in the soft data mode, the controller 250 can be configured to read soft data from the memory corresponding to the first and second codewords, to re-decode the first and second codewords with the first ECC decoder 230 to provide third and fourth results, respectively, and to decode a fourth codeword using the second ECC decoder 240 to provide re-decoded data, wherein the fourth codeword comprises the third and fourth results.

FIG. 4 is a graph of the performance of an example controller utilizing a single iteration of LDPC inner decoding with BCH outer decoding in accordance with certain embodiments described herein. The horizontal axis is the signal-to-noise ratio (SNR) in decibels, and the vertical axis is the codeword failure rate or block error rate (CWER). The input to the LDPC inner decoder is hard data from flash memory.

The open diamonds denote the results using a respective BCH codeword for each LDPC codeword, and the open squares denote the results using a single BCH codeword for four grouped LDPC codewords. As can be seen in FIG. 4, for the single BCH codeword for four LDPC codewords, a codeword error rate (CWER) of 10⁻⁵ is reached at a lower SNR (higher noise) than for the respective BCH codeword for each LDPC codeword. Thus, using a single BCH codeword for four LDPC codewords results in improved performance as compared to the respective BCH codeword for each LDPC codeword. Although specific embodiments have been discussed here where the recovery scheme involves reading soft data and re-decoding the inner codewords, embodiments may utilize other recovery schemes in addition to or in place of such a scheme. For example, another recovery scheme may involve re-decoding the inner codewords by allowing the inner decoder to run more than the particular number of iterations without reading and/or inputting soft data into inner decoder. Other example recovery schemes include, but are not limited to, re-reading the hard data several times and averaging the values, or doing channel calibration and re-reading the hard data.

Various embodiments have been described above. Although this invention has been described with reference to these specific embodiments, the descriptions are intended to be illustrative and are not intended to be limiting. Various modifications and applications may occur to those skilled in the art and all such modifications are intended to be within the appended claims. 

What is claimed is:
 1. A method for error correcting data, the method comprising: reading a first codeword from memory; reading a second codeword from the memory; decoding the first codeword using a first decoder to provide a first result without inputting soft data to the first decoder, wherein the first decoder runs up to a particular number of iterations to provide the first result; decoding the second codeword using the first decoder to provide a second result without inputting soft data to the first decoder, wherein the first decoder runs up to the particular number of iterations to provide the second result; decoding a third codeword using a second decoder to provide decoded data, wherein the third codeword comprises the first result and the second result; and if the decoded data includes an error, performing a recovery scheme.
 2. The method of claim 1, wherein the memory comprises flash memory.
 3. The method of claim 1, wherein decoding the third codeword using a second decoder comprises decoding the third codeword using a Bose-Chaudhuri-Hocquenghem (BCH) decoder.
 4. The method of claim 1, wherein performing the recovery scheme comprises: reading soft data from the memory corresponding to the first and second codewords; and re-decoding the first and second codewords with the first decoder using the soft data to provide third and fourth results, respectively; and decoding a fourth codeword using the second decoder to provide re-decoded data, wherein the fourth codeword comprises the third and fourth results.
 5. The method of claim 1, wherein reading the first and second codewords comprises receiving the first and second codewords at a controller over an interface coupled between the controller and the memory.
 6. The method of claim 1, wherein decoding the first and second codewords using a first decoder comprises decoding the first and second codewords using a low density parity check (LDPC) decoder.
 7. The method of claim 1, wherein reading the first and second codewords comprises: sensing the first codeword from a first plurality of memory cells of the memory; and sensing the second codeword from a second plurality of memory cells of the memory.
 8. The method of claim 1, wherein the particular number of iterations is one.
 9. The method of claim 1, wherein the first codeword comprises a first plurality of user data bits and a first plurality of parity bits, the second codeword comprises a second plurality of user data bits and a second plurality of parity bits.
 10. The method of claim 9, wherein the third codeword further comprises a plurality of checksum bits.
 11. An apparatus comprising: a first error correction code (ECC) decoder configured to decode a first codeword to provide a first result and to decode a second codeword to provide a second result, wherein the decoder is configured to run up to a particular number of iterations to provide each of the results; a second ECC decoder configured to decode a third codeword to provide decoded data, wherein the third codeword comprises the first result and the second result; an evaluation module configured to initiate a recovery scheme responsive to the decoded data including an error.
 12. The apparatus of claim 11, wherein the apparatus comprises a controller.
 13. The apparatus of claim 11, wherein the apparatus comprises a memory device and wherein the memory device includes a controller comprising the first ECC decoder, the second ECC decoder and the evaluation module.
 14. The apparatus of claim 11, wherein the evaluation module is a component of the second ECC decoder.
 15. The apparatus of claim 11, wherein the second ECC decoder comprises a BCH decoder.
 16. The apparatus of claim 15, wherein the first ECC decoder comprises an LDPC decoder.
 17. The apparatus of claim 15, wherein the BCH decoder has a T-correction capability in a range between 20 and
 160. 18. The apparatus of claim 11, wherein the particular number of iterations is one.
 19. The apparatus of claim 11, wherein the second ECC decoder is a component of the evaluation module.
 20. The apparatus of claim 11, wherein the third codeword comprises an outer codeword comprising a plurality of inner codewords including the first and second codewords.
 21. The apparatus of claim 11, wherein the third codeword comprises a number of outer ECC bits and a number of user data bits, wherein the second ECC decoder is configured to use the outer ECC bits to correct errors in the user data bits and wherein the first ECC decoder is configured to use the inner ECC bits to correct errors in the user data bits.
 22. The apparatus of claim 21, wherein the number of inner ECC bits is greater than the number of outer ECC bits
 23. The apparatus of claim 22, wherein the number of inner ECC bits is about 4 times greater than the number of outer ECC bits.
 24. The apparatus of claim 23, wherein the number of inner and outer ECC bits in the third codeword comprises about 10% of a number of bits in a page of memory.
 25. The apparatus of claim 20, wherein the outer codeword comprises a BCH codeword and the inner codewords comprise LDPC codewords.
 26. The apparatus of claim 11, wherein the apparatus further comprises memory, wherein the memory is coupled to a controller comprising the first ECC decoder, the second ECC decoder and the evaluation module, and wherein the controller is configured to read the first and second codewords from the memory while operating in a hard data only mode.
 27. The apparatus of claim 26, wherein the evaluation module being configured to initiate a recovery scheme comprises the evaluation module being configured to switch an operating mode of the controller from the hard data only mode to a soft data mode.
 28. The apparatus of claim 27, wherein while operating in the soft data mode, the controller is configured to: read soft data from the memory corresponding to the first and second codewords; re-decode the first and second codewords with the first ECC decoder using the soft data to provide third and fourth results, respectively; and decode a fourth codeword using the second ECC decoder to provide re-decoded data, wherein the fourth codeword comprises the third and fourth results.
 29. The apparatus of claim 26, wherein the memory comprises a memory device.
 30. The apparatus of claim 29, wherein the memory device comprises a NAND Flash memory device.
 31. The apparatus of claim 30, wherein the NAND Flash memory device is coupled to the controller through an ONFI interface.
 32. A solid state drive comprising: a memory; a first error correction code (ECC) decoder configured to receive encoded information read from the memory in a hard read only mode and to generate a first codeword for the encoded information read from the memory, wherein the first ECC decoder uses a number of iterations less than or equal to a particular number of iterations to generate the first codeword; and a second ECC decoder configured to generate data in response to a second codeword comprising a plurality of the first codewords grouped together, wherein the solid state drive is responsive to at least one bit error of the data by initiating a recovery scheme.
 33. The solid state drive of claim 32, further comprising an evaluation module configured to switch an operating mode of the evaluation module from the hard read only mode to a soft data mode upon the solid state drive initiating the recovery procedure.
 34. The solid state drive of claim 32, wherein the first ECC decoder is a single decoder configured to generate multiple codewords serially.
 35. The solid state drive of claim 32, wherein the first ECC decoder comprises multiple decoders configured to generate multiple codewords in parallel. 